The present invention relates to an erase method for nonvolatile semiconductor storage devices capable of preventing disturb at erasing, particularly, in floating gate type nonvolatile semiconductor storage devices, and also relates to a row decoder circuit for fulfilling the method.
In recent years, with the trend toward higher integration of flash memories, there has been a demand for lower power consumption. For this purpose, a variety of attempts to achieve lower power consumption have been made by using the FN (Fowler-Nordheim) tunneling phenomenon for program and erase operations. Flash memories using the FN tunneling phenomenon for program and erase operations like this are called FN-FN type flash memories.
Meanwhile, the flash memories can be classified also depending on differences in the structure of memory cell array or the like. The major four classes, as have been announced from various companies, are listed below:
[1] AND type flash memories reported in Technical Report of IEICE (the Institute of Electronics, Information and Communication Engineers of Japan), ICD93-128, p. 37, 1993, xe2x80x9cAND Type Cell for 3V Single Power Supply 64 Mbit Flash Memoriesxe2x80x9d;
[2] DINOR type flash memories reported in Technical Report of IEICE, ICD93-26, p. 15, 1993, xe2x80x9c3V Single Power Supply DINOR Type Flash Memoriesxe2x80x9d;
[3] DuSNOR type flash memories reported in Technical Digest, pp. 263-266, 1995, xe2x80x9cA Novel Dual String NOR (DuSNOR) Memory Cell Technology Scalable to the 256 Mbit and 1 Gbit Flash Memoriesxe2x80x9d; and
[4] ACT (Asymmetrical Contactless Transistor) type flash memories reported in IEDM Technical Digest, pp. 269-270, 1995, xe2x80x9cA New Cell Structure for Sub-quarter Micron High Density Flash Memoryxe2x80x9d or
in Technical Report of ICICE, ICD97-21, p. 37, 1997, xe2x80x9cDiscussion on Sense Systems for ACT Type Flash Memoriesxe2x80x9d.
In these flash memories, which are electrically programmable and erasable on memory cells, a voltage is applied to the drains/sources or gates of select cells while a voltage is applied also to the drains/sources or gates of non-select memory cells, for program and erase operations. During these operations, there is a possibility that mis-reads occur because threshold of the non-select memory cells would be changed by an effect of the voltage application.
In recent years, a system in which a negative voltage is applied to the substrate (well), has begun to be used in order to reduce the absolute values of voltages used inside the flash memory during the erasing. When a voltage is applied to the substrate (well) in program and erase operations, this applied voltage would cause non-select memory cells to be put into a light erased state as described above, adversely affecting the threshold of the non-select memory cells. Hereinafter, such a phenomenon will be referred to as substrate disturb. This substrate disturb tends to grow stricter as the flash memory goes larger capacity.
This substrate disturb is explained by taking the ACT type flash memory as an example. First, the principle of operation of the ACT type flash memory is explained based on a memory cell shown in FIG. 19.
The ACT type flash memory is so constructed that a control gate 1, an interlayer insulator 2, a floating gate 3 and a tunnel oxide 4 are formed in layers so as to stretch over a drain 6 and a source 7 provided in a substrate (P-type well) 5. It is noted that the drain 6 and the source 7 have different donor concentrations. Then, in the program operation in which electrons are pulled out from the floating gate 3, a negative voltage of xe2x88x928 V is applied to the control gate 1 and a positive voltage of +5 V is applied to the drain 6 so that the source 7 is put into a floating state, where the electrons are pulled out from the floating gate 3 by the FN tunneling phenomenon. As a result, the threshold of the memory cell to be programmed is lowered to about 1.5 V.
Also, in the erase operation in which electrons are injected into the floating gate 3, a positive voltage of +10 V is applied to the control gate 1, a negative voltage of xe2x88x928 V is applied to the source 7 and a negative voltage of xe2x88x928 V is applied to the drain 6, where the electrons are injected into the floating gate 3 by the FN tunneling phenomenon. As a result, the threshold of the cell to be erased is increased so as to rise to about 4 V or more. Like this, the ACT type flash memory is an FN-FN type flash memory.
Further, in the read operation, a voltage of 3 V is applied to the control gate 1, a voltage of 1 V is applied to the drain 6 and a voltage of 0 V is applied to the source 7, where a current flowing through the cell is sensed separately by a sense circuit, by which data is read out.
Table 1 lists the applied voltages for the program, erase and read operations.
Next, for explanation of the substrate disturb at erasing, the erase operation is described in more detail with an array structure shown in FIG. 1. As schematically shown in FIG. 1, the array structure of the ACT type flash memory is a virtual-ground type array structure in which one bit line BL is shared by two memory cells. Then, by sharing the individual bit lines and by using a diffusion layer for sub-bit lines (SBL0, SBL1, SBL2, . . . ), the number of contacts is reduced so that the array area is considerably reduced, thus making it possible to achieve high integration.
It is noted here that BL0-BL4096 are main bit lines, SBL0-SBL4096 are sub-bit lines formed of the diffusion layer (hierarchically different from the main bit lines BL0-BL4096), and WL0-WL63 are word lines. Also, SG0 and SG1 are gate lines of select transistors for selecting a block 1 comprised of word lines WL0-WL31 and block 2 comprised of word lines WL32-WL63. It is noted that blackened square symbols in the figure represent contact portions between the main bit lines BL and the sub-bit lines SBL. In addition, two sides of the drain and the source to be connected to a sub-bit line SBL common to neighboring memory cells are different in donor concentration from each other.
FIG. 21 schematically shows a cross section of an ACT type flash memory device, where from above to below, a word line (control gate 1) WL, an interlayer insulator 2, a floating gate (FG) 3 and a sub-bit line (diffusion layer) SBL are arranged in a layered structure. The sub-bit line SBL provided commonly under end portions of neighboring floating gates 3, 3 is different in donor concentration between the drain 6 side and the source 7 side.
In the case of the ACT type flash memory having the above constitution, the erase operation is performed on a block-by-block basis. That is, for erasing, in order to raise the threshold of the memory cell, a voltage of +10 V is applied to the word lines WL0-WL31 connecting to the control gate 1 of a select block (block 0 in this case). Further, a voltage of xe2x88x928 V is applied to the substrate (well) 5 and the main bit lines BL0-BL4096. In this case, the voltage of the gate line SG0 is 0 V, making the select transistors on, so that a voltage of xe2x88x928 V is outputted to the sub-bit lines SBL0-SBL4096 formed of the diffusion layer. As a result, a high electric field is generated between the floating gate 3 and the channel of each memory cell, so that electrons are injected into the floating gate 3 by the FN tunneling phenomenon, with the result that the threshold of the memory cell rises to 4 V or more.
Meanwhile, in a non-select block (block 1 in this case), Vss (0 V) is applied to the word lines WL32-WL63. Also, xe2x88x928 V is applied to the gate line SG1, making the select transistors off. Accordingly, the sub-bit lines SBL0-SBL4096 connected to the select transistors associated with the gate line SG1 come to a floating state. In this case, since the substrate (well) 5 is common to all the memory cells, xe2x88x928 V is applied thereto so that an electric field not so high as that of the select block is generated also between the floating gate 3 and the substrate (well) 5. As a result, electrons are injected into the floating gate 3.
Such injection of electrons into the floating gate 3 in the non-select block noticeably occurs at memory cells of low threshold in the programmed state (i.e., memory cells of data xe2x80x9c0xe2x80x9d).
Now the substrate disturb is discussed with respect to a 64 M flash memory containing 512 blocks each having a block size of, for example, 16 KB. In the case where each block is reprogrammed one million times, given each erase time of 2 ms, the disturb time, which is a total of time durations of application to the non-select block, can be expressed by the following Equation (1):
511xc3x971,000,000 timesxc3x972 ms≈106 secxe2x80x83xe2x80x83(1)
FIG. 20 shows an example of the substrate disturb in by a conventional erase method. As can be understood from the figure, after 106 sec., which is the disturb time, the threshold of the memory cell in the programmed state (data xe2x80x9c0xe2x80x9d) becomes above 3 V, higher than the Ref (reference) voltage of 3 V in the sense circuit at a read. Thus, data xe2x80x9c0xe2x80x9d would be mis-sensed as data xe2x80x9c1xe2x80x9d, resulting in occurrence of a mis-read.
Also, in the case where a negative voltage is applied to the substrate (well) 5 at erasing as described above, there arises a need for a negative voltage charge pump that boosts the power supply voltage to generate a negative voltage to be applied to the substrate (well) 5. Then, because of quite large capacity accompanying the substrate (well) 5, the charge pump for generating this negative voltage needs to have quite large power. For the formation of a 64 M flash memory, which involves a capacity as much as 32000 pf that accompanies the substrate (well) 5, given that the rise time at erasing is 100 xcexcs (assuming that the erase pulse time is 1 ms and that the rise time takes 10%), then an electric current of about 30 mA is required.
Further, the charge pump efficiency is generally low and, in particular, a charge pump that generates negative voltage has an efficiency of 10% or so, with the result of an increased area. Therefore, in order to implement the charge pump, the layout area for the charge pump is about 5% relative to the chip area, the layout area of the charge pump being a considerably large one.
Such a nonvolatile storage device designed to relax the substrate disturb as well as the increase in the layout area of the charge pump due to an increase in the well capacity is disclosed in Japanese Patent Laid-Open Publication HEI 9-162373. In the nonvolatile storage device disclosed in Japanese Patent Laid-Open Publication HEI 9-162373, for example, the well of a 64 M flash memory is divided into 16 in the row direction. By this division, the disturb time results in
31xc3x971,000,000 timesxc3x972 ms=62,000 sec.
Therefore, as can be understood from FIG. 20, even after 62,000 sec., which is the disturb time, the threshold of the memory cell in the programmed state holds a state of about 2 V, not higher than the Ref voltage of the sense circuit at a read, thus making a normal read achievable. also, the capacity of each divisional well is about 2000 pf, so that the current supply power necessary for the charge pump is also reduced. Therefore, the area necessary for the formation of the charge pump is also reduced to 1% or lower relative to the chip area.
However, the nonvolatile storage device disclosed in Japanese Patent Laid-Open Publication HEI 9-162373 has the following problems. That is, isolation of the well would give rise to the need of providing an isolation region, causing the area of the memory cell array to increase, where the chip area would increase 8% or so. Due to this, in the method by isolating the well, although a margin can be saved for substrate disturb, there is a problem that the whole chip area would be increased.
Still, the disturb is not completely eliminated, and voltage applications for rewriting such as programming and erasing would act as a stress, so that, for example, executing one million times of rewriting would cause hole trap or other defects to occur. Then, because of these defects, there can appear some memory cells whose threshold in the programmed state go higher than 3 V, which is the Ref voltage in the sense circuit.
Accordingly, an object of the present invention is to provide an erase method for nonvolatile semiconductor storage devices capable of preventing mis-reads due to substrate disturb at erasing and of reducing the current of the negative voltage charge pump for the generation of the voltage applied to the substrate (well) and also reducing the layout area for the charge pump, as well as to provide a row decoder circuit for realizing the erase method.
In order to achieve the object, there is provided an erase method for a nonvolatile semiconductor storage device in which floating gate field effect transistors each having a control gate, a floating gate, a drain and a source and being electrically information programmable and erasable are arrayed in a matrix shape on a substrate or well, and which comprises a plurality of row lines connected to the control gate of each of floating gate field effect transistors arrayed along a row direction, and a plurality of column lines connected to the drain and source of each of floating gate field effect transistors arrayed along a column direction, the method comprising:
using the Fowler-Nordheim tunneling phenomenon for both programming and erasing; and
for erasing, applying a negative first voltage to the substrate or well and applying a positive voltage to select row lines, while applying a negative second voltage to non-select row lines.
With this constitution, for an erase of the nonvolatile semiconductor storage device with the use of the FN tunneling phenomenon, a negative voltage is applied to both the substrate (well) and non-select row lines. Therefore, by setting the applied voltage for the substrate (well) and the applied voltage for the non-select row lines so that the erase operation is not affected by any substrate disturb, any increase of the threshold voltage of programmed memory cells can be prevented even if the nonvolatile semiconductor storage device is iteratively rewritten. As a result, mis-reads of the programmed memory cells can be prevented.
Further, the voltage difference between the. substrate (well) and the non-select row lines is reduced, so that the electrical capacity between the substrate (well) and the non-select row lines is reduced. As a result, the layout area of the charge pump that supplies the negative voltage to the substrate (well) can be reduced.
In one embodiment of the present invention, the negative second voltage has an absolute value not larger than an absolute value of the negative first voltage.
With this constitution, since the absolute value of the negative second voltage is set lower than the absolute value of the negative first voltage, misoperations of non-erase memory cells can be prevented. Further, by setting the absolute values of the negative first and second voltages equal to each other, the substrate disturb can completely be prevented.
Further, the voltage difference between the substrate (well) and the non-select word lines can be made smaller than conventional, and the electrical capacity between the substrate (well) and the non-select word lines can be reduced so that the current necessary for charging and recharging to the capacity can be reduced. Therefore, supply power of the charge pump that generates the negative voltage supplied to the substrate (well) can be reduced so that the area of the charge pump can be reduced.
Also, there is provided a row decoder for applying a select voltage and a non-select voltage to select word lines and non-select word lines of a nonvolatile semiconductor storage device, the select word lines and the non-select word lines being determined according to an address signal, on a mode-by-mode basis for each of a program mode, a read mode and an erase mode, the row decoder comprising:
control voltage output means for, on the mode-by-mode basis, outputting a control voltage responsive to select/non-select information which is determined according to the address signal;
select voltage output means for, on the mode-by-mode basis, outputting a select voltage responsive to a select state which is determined according to the address signal;
non-select voltage output means for, on the mode-by-mode basis, outputting a non-select voltage responsive to a non-select state which is determined according to the address signal; and
applied voltage select means for, in the erase mode, selecting either one of the select voltage derived from the select voltage output means or the non-select voltage derived from the non-select voltage output means according to the control voltage derived from the control voltage output means, and outputting the selected voltage au to select word lines while outputting the non-selected voltage to non-select word lines.
With this constitution, in the erase mode, a control voltage responsive to select/non-select information is outputted according to the address signal by the control voltage output means. Then, the select voltage derived from the select voltage output means is outputted to select word lines according to the control voltage by the applied voltage select means. Also, the non-select voltage derived from the non-select voltage output means is outputted to non-select word lines. In this case, the voltage applied to the substrate (well) is given by the negative first voltage, the select voltage is given by the positive voltage, the non-select voltage is given by the negative second voltage, and the values of the two negative voltages are set so that the erase operation is not affected by any substrate disturb. By these settings, increase of the threshold voltage of programmed memory cells due to iterated rewriting can be prevented. As a result, mis-reads of the programmed memory cells can be prevented.
Also, there is provided a row decoder for applying a select voltage and a non-select voltage to select word lines and non-select word lines of a nonvolatile semiconductor storage device, the select word lines and the non-select word lines being determined according to an address signal, on a mode-by-mode basis for each of a program mode, a read mode and an erase mode, the row decoder comprising:
control voltage output means for, on the mode-by-mode basis, outputting a control voltage responsive to select/non-select information which is determined according to the address signal;
high voltage output means for, on the mode-by-mode basis, outputting a high voltage not less than a specified voltage responsive to a select state which is determined according to the address signal;
low voltage output means for, on the mode-by-mode basis, outputting a low voltage lower than the high voltage responsive to a non-select state which is determined according to the address signal; and
applied voltage select means for, in the erase mode, selecting either one of the high voltage derived from the high voltage output means or the low voltage derived from the low voltage output means according to the control voltage derived from the control voltage output means, and outputting the high voltage to select word lines as the select voltage while outputting the low voltage to non-select word lines as the non-select voltage.
With this constitution, in the erase mode, a control voltage responsive to select/non-select information is outputted according to the address signal by the control voltage output means. Then, the high voltage derived from the high voltage output means is outputted as the select voltage to select word lines according to the control voltage by the applied voltage select means. Also, the low voltage derived from the low voltage output means is outputted as the non-select voltage to non-select word lines. In this case, the voltage applied to the substrate (well) is given by the negative first voltage, the select voltage is given by the positive voltage, the non-select voltage is given by the negative second voltage, and the values of the two negative voltages are set so that the erase operation is not affected by any substrate disturb. By these settings, increase of the threshold voltage of programmed memory cells due to iterated rewriting can be prevented. As a result, mis-reads of the programmed memory cells can be prevented.
Further, the output voltage from the high voltage output means is set normally higher than the output voltage from the low voltage output means. Therefore, the select operation by the applied voltage select means for selection of the output voltages from the high voltage output means and the low voltage output means is simplified, compared with the case of an embodiment of the invention in which the relationship of magnitude between the output voltage from the select voltage output means and the output voltage from the non-select voltage output means varies from mode to mode. Therefore, the constitution of the applied voltage select means becomes simpler than that of the foregoing embodiment of the invention, so that occupancy area of the applied voltage select means is reduced.
In one embodiment of the present invention, in the erase mode, the select voltage is a positive voltage, while the non-select voltage is a negative voltage; and
an absolute value of the non-select voltage is not larger than an absolute value of the negative voltage applied to the substrate or well of the nonvolatile semiconductor storage device.
With this constitution, in the erase mode, since the absolute value of the non-select voltage applied to the non-select word lines is smaller than the absolute value of the voltage applied to the substrate (well), misoperations of non-erase memory cells can be prevented. Further, by setting the absolute values of the voltage applied to the substrate (well) and the voltage applied to the non-select word lines equal to each other, the substrate disturb can completely be prevented.